Main / Puzzle / Riviera-pro
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Riviera-PRO™ addresses verification needs of engineers crafting tomorrow's cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench. To download a vendor library, pre-compiled for Riviera-PRO, you will need to log into your user account at kelloughenterprises.com, proceed to DOWNLOADS page. 18 Apr - 9 min - Uploaded by Ian Gibbins Demonstration of Aldec Riviera-PRO logic simulator.
28 Feb - 6 min - Uploaded by aldecinc The Coverage tools available in Riviera-PRO can analyze Code Coverage, Functional. 12 Apr - 7 min - Uploaded by aldecinc Design Profiling is a feature that will monitor CPU utilization during simulation. Profiling your. Riviera-PRO is a multi-platform, high-performance, mixed-language RTL and gate-level simulator for ASIC and FPGA designs. It includes advanced debugging .
Riviera-PRO addresses the verification requirements of engineers targeting large gate-count FPGAs, ASICs and System-on-Chip devices. It gives engineers the. Description. Riviera-PRO™ is a high-performance ASIC and large FPGA verification solution that is optimized for long simulation runs and batch processing.